Power MOSFETs (metal oxide semiconductor (MOS) field effect transistors (FET)) are used, for example, as electric switches for high frequency PWM (pulse width modulation) applications such as voltage regulators and/or as load switches in power applications. When used as load switches, where switching times are usually long, cost, size and on-resistance of the switches are the prevailing design considerations. When used in PWM applications, the transistors must exhibit small power loss during switching, which imposes an additional requirement—small internal capacitances—that make the MOSFET design challenging and often times more expensive. Special attention has been paid to the Gate-to-Drain (Cgd) capacitance, as this capacitance determines the voltage transient time during switching and is the most important parameter affecting the switching power loss.
Examples of prior art laterally diffused power MOSFET devices are provided in U.S. Pat. No. 5,949,104 to D'Anna et al. and U.S. Pat. No. 6,831,332 to D'Anna et al., the entirety of which are hereby incorporated by reference herein. Both devices use thick epitaxial layers to achieve the high breakdown voltage (>60V) required for the target RF applications. To minimize the parasitic source inductance in the assembly, both devices are designed on P+ substrates leading the source electrode to the back side of the die. The thick epitaxial layer and P+ substrate result in a high on resistance (Rds,on) of the device, which is not acceptable for power management applications.
Another prior art LDMOS device is disclosed in U.S. Pat. No. 6,600,182 to Rumennik, entitled “High Current Field-Effect Transistor.” The Rumennik device includes a drain region that has a first portion that extends vertically through the epitaxial layer to connect to the substrate and a second portion that extends laterally along the top surface of the device. The device has low specific on-resistance and supports high current flow. However, the breakdown voltage of the device is highly dependent on the location of the first portion of the drain region, which narrows the manufacturing tolerances for the device.
There remains a need for a LDMOS design that exhibits improved device performance (Rds,on and Cgd) with improved manufacturability.